module SOC_top(
    input clk,
    input rst_n,

    input   [2:0]       data_addr,
    input               data_write_en,
    input               data_read_en,
    input   [127:0]     data_write_data,
    output  [127:0]     data_read_data
);     
    wire   [4:0]    CMD;
    wire   [127:0]  intxt;
    wire   [127:0]  outtxt;

  
    address_map  u_address_map (
        .clk                     ( clk               ),//
        .rst_n                   ( rst_n             ),//
        .data_addr               ( data_addr         ),//
        .data_write_en           ( data_write_en     ),//
        .data_read_en            ( data_read_en      ),//
        .data_write_data         ( data_write_data   ),//
        .keyexprdy               ( keyexprdy         ),//
        .encdecrdy               ( encdecrdy         ),//
        .outtxt                  ( outtxt            ),//

        .data_read_data          ( data_read_data    ),//
        .CMD                     ( CMD               ),//
        .load                    ( load              ),//
        .intxt                   ( intxt             ),//
        .key                     (                )
    );

    aes_top  u_aes_top (
        .clk                     ( clk         ),//
        .rst_n                   ( rst_n       ),//
        .load                    ( load        ),//
        .CMD                     ( CMD         ),//
        .intxt                   ( intxt       ),//

        .keyexprdy               ( keyexprdy   ),//
        .encdecrdy               ( encdecrdy   ),//
        .outtxt                  ( outtxt      )//
    );

endmodule